I. Field of the Invention
II. Description of the Related Art
Transmission of voice by digital techniques has become widespread, particularly in long distance and digital radio telephone applications. If speech is transmitted by simply sampling and digitizing, a data rate on the order of 64 kilobits per second (kbps) is required to achieve the speech quality of conventional analog telephones. However, through the use of speech analysis, followed by the appropriate coding, transmission, and synthesis at the receiver, a significant reduction in the data rate can be achieved. Apparatus that perform speech analysis and coding at the transmitter and synthesis at the receiver are known as vocoders.
The recent development of digital cellular telephone standards and systems have spurred the need for these vocoders. The desire for advanced vocoding algorithms which use the available transmission bandwidth more efficiently and reproduce the source speech more accurately at the receiver has increased the need for processors with greater computational capacity needed to perform these more complex vocoding algorithms.
Vocoders take advantage of long term and short term redundancies in speech, requiring computationally intensive numerical operations. Some of these operations include long sequence convolutions, matrix inversions, long sequence correlations, and so on. For these operation to be conducted in real time without incurring intolerable coding and decoding delays in the transmission of speech requires powerful computational resources.
The emergence of digital signal processors (DSPs) was an important factor in enabling the real time implementation of vocoder algorithms. DSPs are highly efficient in performing the arithmetic operations common to vocoder algorithms. Advances in DSPs have increased their computational capacity to rates of 40 million instructions per second (MIPS) and above.
The vocoding algorithm used for exemplary purposes is the variable rate code excited linear prediction (CELP) algorithm detailed in copending patent application Ser. No. 08/004,484, filed Jan. 14, 1993, entitled "Variable Rate Vocoder" and assigned to the assignee of the present invention. The material in the aforementioned patent application is incorporated by reference herein.
Shown below in Table I is a run time profile for a single 20 millisecond speech frame, of the encoding portion of the exemplary vocoding algorithm, as implemented using a typical DSP. Because the encoding portion of the exemplary vocoding algorithm requires significantly more processing than does the decoding portion, only the encoding process is detailed in Table I. The DSP referred to in Table I is clocked at 40 MHz and performs arithmetic operations and other operations, each in one or more clock cycles, depending on the operation. The first column presents the main operations of the exemplary vocoding algorithm. The second column presents the number of clock cycles required to accomplish each particular operation of the vocoder algorithm using the exemplary DSP. The third column presents the percentage of total processing required by the particular operation. The exemplary vocoding algorithm requires that all operations be performed within 20 milliseconds for real time operation of the exemplary vocoding algorithm. This places a requirement on the DSP chosen to implement the algorithm, such that the DSP be capable of operation at a clock rate at or above that required to complete the required processing within the 20 millisecond frame. For the typical DSP described by Table I, this restricts the number of clocks to 800,000.
TABLE I ______________________________________ 40 MHz Routine clocks % of Total ______________________________________ LPC Analysis 24810 3.89 LPC to LSP Conversion 48780 7.65 Rate Decision 330 0.05 LSP Quantization 660 0.10 Unquantize LSP 1110 0.17 LSP/LPC Interpolation 34590 5.42 Pitch Search 225570 35.36 Codebook Search 262380 41.13 Synthesis 34230 5.37 Packing 5490 0.86 Total 637950 100.00 ______________________________________
As can be seen by Table I the pitch search and codebook search operations consume over 75 percent of the processing time in the encoding portion of the vocoder algorithm. Since the majority of the computational load lies within these two search algorithms, the primary objective of an efficient ASIC designed to perform vocoding is to reduce the number of clock cycles required to perform these two operations.
The method and apparatus of the present invention greatly decreases the number of instruction cycles necessary to perform these search operations. The present invention provides further methods and apparatus that are optimized for performing more efficiently operations that are of particular significance to vocoding algorithms. The application of the methods and apparatus of the present invention are not limited to performing the exemplary vocoding operation or even to performing speech encoding or decoding. It is envisioned that the methods and apparatus can be applied to any system that utilizes digital signal processing algorithms such as echo cancellers and channel equalizers.